This invention relates generally to data processing systems including a host computer coupled through cache buffer memory to a magnetic tape drive subsystem, and more particularly to a method and apparatus for temporarily storing multiple data records within the cache buffer memory such that overall system performance is optimized.
Various methods and apparatus have been utilized to temporarily store multiple data records in data processing systems having a host computer and a long term storage device such as a magnetic tape drive subsystem. Typical magnetic tape drives in the past were utilized in a start-and-stop mode of operation at approximately 50 inches per second. To increase performance for host throughput, a 100 inches per second "streaming" tape drive was developed. Data transferred from a 100 ips tape drive was developed. Data transferred from a 100 ips tape drive can transfer at twice the rate of a 50 inches per second tape drive. However a streaming drive has the disadvantage that it cannot stop (and later start) within the gap, but must do extra repositioning in order to be ready for the next start. This extra repositioning causes large delays for the host compared to a 50 inches per second start-and-stop tape drive. Therefore, if the host computer was too slow to reinstruct the tape drive subsystem, unnecessary stoppage and subsequent repositioning was required thereby reducing overall system performance.
Because the relative transfer rates of data through the typical host computer and tape drive subsystem differed substantially, the use of a cache buffer in such data processing systems became increasingly popular. The use of such cache buffers are well known and need little explanation. However, the management and control of such buffers in order to optimize overall data processing system performance has encountered many variations. One method uses two address registers, one for fill and one for drain, together with a counter which counts the number of bytes in the record. A record is prevented from overwriting another by never allowing the counter to exceed a maximum byte count.
Another method, compatible with IBM 3480 type data processing systems, utilizes a register to indicate the fill address while data is going into the buffer, an address indicative of the start of a record, and a drain address register for use in conjunction with a counter. During fill operations with such systems, the fill address register is used to feed a data record into the buffer, and the start of record address is utilized to indicate when the buffer is full at the time that the fill address register equals the start of record address. On the other hand, during drain of data, or when data is coming out of the buffer, such systems increment the drain address register and decrement the byte count obtained by the counter during the filling of the record, such that when the byte count equals zero the drain operation is finished. One major drawback to the use of such systems, however, is that the number of records available to be put into the buffer is limited by the memory space available in a microprocessor which manages the buffer, the memory space being allocated to the counter for keeping track of the number of bytes.
Yet another prior art approach utilizes a method similar to that described above, but also inputs a cyclic redundancy check (CRC) character for each data record in the microprocessor memory space after the indication of the number of bytes in the respective record. This method utilizes even more microprocessor memory space than the previously described method, and thus restricts the use of the microprocessor managing the buffer from other, more important operations.
Another prior art approach eliminates the use of a counter which counts the number of bytes in each record by placing a stop bit at the end of each record. That approach, while useful during read operations, is somewhat restricted during write operations due to its potential for overwriting of data records. It would therefore be desirable to provide controls for a cache buffer memory which optimizes performance of the data processing system by temporarily storing multiple data records in the cache buffer such that they may be readily accessed upon command by the host computer.